The present invention generally relates to a semiconductor device and a manufacturing method thereof, and more specifically to a semiconductor device and also a method for manufacturing such a semiconductor device that a bipolar transistor and MOS transistors are assembled on the same substrate.
In the conventional semiconductor devices as described in the preamble, both higher velocities and higher integration of the overall semiconductor devices have been developed. That is to say, in conjunction with the fine treatment of the MOS transistors, the bipolar transistor is similarly manufactured with higher performances.
In case that a MOS transistor is fabricated, a gate electrode thereof is formed, and then is used as a portion of a mask for forming a drain layer and a source layer, taking account of such a fact that this gate electrode is not removed during the subsequent manufacturing step. A so-called "self-alignment" method has been utilized. Since there is no problem to cause the mask shifts with employment of such a self-alignment method, the distance between the drain layer and source layer can be considerably reduced.
On the other hand, even in a bipolar transistor, a method similar to the above-described self-alignment method has been utilized. In other words, a base electrode constructed of a polycrystal silicon layer containing an impurity (for instance, a p type impurity) is formed which surrounds a region where an emitter is formed, the above-described impurity is diffused from a semiconductor plane which is exposed at a center of this base electrode, and simultaneously an impurity contained within the base electrode is also diffused in the thermal (heat) treatment so as to form a base layer. Then, an emitter electrode made of a polycrystal silicon layer containing an impurity (for instance, an n type impurity) is formed in connection with the above-described semiconductor plane which is exposed from the base electrode, an impurity contained in the emitter electrode is diffused by a thermal treatment so as to fabricate an emitter layer within the base layer (refer to pages 748 to 751, International Electron Device Meeting technical digest).
Then, very recently, when the above-described bipolar transistor is formed together with the MOS transistors, these elements have been manufactured by the self-alignment method, and the gate electrodes thereof have been formed by the polysilicon layers into which an impurity (i.e., an impurity having a conductivity type different from a semiconductor layer in which a channel layer is formed). This is because when the polycrystal silicon layer is used as the gate electrode, there are particular advantages that an oxide film is formed on a side wall portion thereof so as to achieve the insulation, such a drawback that metal particles are diffused to a side of a semiconductor substrate can be prevented, and also an easy treatment and higher reliabilities can be realized.
However, in the thus formed semiconductor devices, in case that each of the MOS transistors is of the same channel types, for instance, n channel types, all of the impurities contained in the polycrystal silicon for constituting the gate electrode thereof are of the same n types. As an example where the conductivities of the gate electrodes are the same, there are described in JP-A-60-254653 and JP-A-63-193558 (EP-A-281711). When a bipolar transistor is of an n p n type, it is different from a p type impurity contained in polycrystal silicon for constituting a base electrode thereof. This implies that there is an advantage such that the n-type polycrystal silicon layer functioning as the gate electrodes of each of the MOS transistors can be fabricated in the same manufacturing step. However, since each of the n type polycrystal silicons must be separated from each other at a distance longer than a predetermined distance in order to establish an electrical isolation, there is a limitation in a minimum distance for this separating distance.